Silicon Bring-Up

It has been a while since my previous post, and a lot has happened since then. Specifically, Claude Code and Codex has taken away all the fun of working on software projects, and that’s why this post is about ASIC validation.

At post-silicon stage, the chips are already manufactured and fixing bugs at this stage might lead to a respin. Hopefully ASIC is verified well at this point.

First we designed a PCB to connect to the chip.

Then we connected the PCB to power supply, oscilloscope, and an Xilinx FPGA (to generate and observe the test vectors). This FPGA is very nice, it has ARM CPU cores that runs Linux and you can connect it to the Internet.

The testing sequence is clock generator → DFT scan chain → chip functionality. Somewhat similar to software testing - making sure that things more likely to work actually work first. And it feels great when DFT works, since it can be impossible to work-around bugs when DFT itself does not work.

And then the chip actually works! All the problems we encountered are actually setup bugs (e.g. wrong pins in Xilinx Vivado pins setup vs on the PCB). We had a Schmoo plot about which frequencies and voltages the chip works correctly at.